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出 处:《半导体技术》2015年第5期333-337,363,共6页Semiconductor Technology
基 金:国家科技重大专项资助项目(2014ZX02302002);国家高技术研究发展计划(863计划)资助项目(2011AA010403)
摘 要:研究并设计了一款5 Gbit/s大摆幅电压模发送器,输出信号差分眼图高度可达1.2 V。工作在1.2 V电压下的输出驱动器由28个相同的子驱动器并联而成,且每个子驱动器都包含权重按照二进制关系递增的4个驱动单元,从而实现了去加重控制与阻抗校正相互独立。为了使输出驱动器的阻抗与传输线的特征阻抗匹配,提出了一种数模混合负反馈环路的阻抗自校正电路,对上拉和下拉部分电阻分别进行校正,实现了5%的校正精度和±40%的校正范围,且回波损耗(S11)在10 GHz时小于-15 d B。设计采用55 nm CMOS工艺流片,面积为320μm×255μm。数据率为5 Gbit/s时,功耗为51.81 m W,总的输出抖动为4.3 ps。A 5 Gbit/s high-swing voltage-mode transmitter was studied and designed,exhibiting a1. 2 V differential eye height. The output driver operated at 1. 2 V is composed of 28 identical parallel connected slices with four binary-weighted segments,so that the de-emphasis control is independent of the impedance self-calibration. In order to make the impedance of the output driver match the characteristic impedance of the transmission line,a digital-analog hybrid negative feedback loop impedance selfcalibration circuit was proposed,and the impedances of the pull-up branches and pull-down branches were controlled separately. The calibrated precision can reach to 5% and the calibrated range can reach± 40%,the return loss( S11) is less than-15 d B when the frequency is 10 GHz. The chip was fabricated in a 55 nm CMOS technology and occupied 320 μm × 255 μm. The power consumption is 51. 81 m W and the total output jitter is 4. 3 ps at 5 Gbit/s.
分 类 号:TN402[电子电信—微电子学与固体电子学]
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