低压高速鉴频鉴相器的设计  

Design of Phase Frequency Detector with High speed under low voltage supply

作　　者：韩婷婷[1] 田密[1] 王志功[1] 徐建[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096

出　　处：《中国集成电路》2015年第5期53-56,共4页China lntegrated Circuit

摘　　要：本文分析了传统的鉴频鉴相器(PFD)的非理想效应,提出了一种新型的高速低压鉴频鉴相器。该设计采用NSTSPC触发器,进行前置双模式复位,从而在较低的工作电压和较高的鉴相频率情况下,很好的抑制死区和第四态的出现,有接近正负2π的鉴相范围和较好的线性度。电路采用了CSMC 0.35um CMOS工艺进行设计。仿真结果显示该PFD可在2.4 V电压、250 MHz频率下实现正确的线性鉴频鉴相功能,工作中平均消耗电流为30u A。In this article, traditional phase frequency detector （ PFD ） and its non-ideal effects were reviewed, and a new type of PFD with high speed under low voltage supply were proposed. The proposed PFD employs NSTSPC flip-flop and applies dual-mode pre-reset. Therefore, it can operate under high frequency and 10w voltage supply. moreover, it realizes the phase-detection range of （ -2π, 2π）with good phase-detection linearity, and inhibits the arising of dead zone and the fourth state. The proposed PFD was designed in CSMC 0.35urn CMOS process. Simula- tion results have shown that the PFD has a proper operation in the frequency of 250 MHz under 2.4 V voltage supply with an average current consumption of 30uA.

关 键 词：高速 死区 

分 类 号：TN763.3[电子电信—电路与系统]