基于Multisim行扫描AFC锁相环电路仿真设计  

Simulation Design of Line Scanning AFC PLL Circuit Based on Multisim

作　　者：李宏恩[1] 

机构地区：[1]长治医学院生物医学工程系,山西长治046000

出　　处：《电子科技》2015年第5期105-107,共3页Electronic Science and Technology

摘　　要：锁相环电路具有良好的相位误差控制功能,可实现电路输入信号与输出信号频率之间的同步。基于设计一种行扫描锁相环电路,采用EDA仿真软件Multisim2001,利用Multisim强大的电路设计和仿真功能,完成对锁相环电路的设计。仿真结果表明,所设计电路实现了对相位的锁定功能,同时依托multisim灵活简便的仿真环境,还可通过改变元件参数,并结合观察各点波形的变化,而找到电路的最佳锁相范围数据,为PCB设计与制作节省了设计成本。The phase-locked loop（PLL） circuit has extensive applications in various electronic devices. It can control the phase error and implement frequency synchronism between the input signal and output signal. To design a line scanning AFC PLL circuit, Multisim2001, which is powerful in circuit design and simulation, is used. Simulation results show that the circuit designed has the function of phase locking. And because of the simple and flexible simulation environment of Muhisim, the optimal phase locking range can be obtained by changing the parameters of the devices and observing the changes in waveform of each point, thus saving cost for PCB design and manufacturing.

关 键 词：MULTISIM2001 行扫描 锁相环 AFC 

分 类 号：TN702[电子电信—电路与系统]