基于NoC的众核处理器可靠性仿真分析研究  

Research on Reliability Simulation of No C Based Many-core Processors

作　　者：杨文顶 覃志东[1] 

机构地区：[1]东华大学计算机科学与技术学院,上海201620

出　　处：《智能计算机与应用》2015年第2期4-8,共5页Intelligent Computer and Applications

基　　金：中央高校基本科研业务费专项基金(11D11209)

摘　　要：随着半导体制造工艺的发展,众核芯片上的晶体管密度不断增加,随之而来的寿命可靠性问题日益严重。为了准确评估芯片的可靠性,本文提出了一种基于蒙特卡洛方法的系统级可靠性仿真框架,并在此基础上研究了No C通信架构对可靠性的影响。实验结果表明,如果不考虑众核芯片的No C通信结构,系统级可靠性评估的相对偏差最高可达到60%左右。With the development of semiconductor manufacturing,the transistor density on many- core chips increases relentlessly and causes significant lifetime reliability problem. To estimate the chip reliability accurately,this paper proposes a system reliability simulation framework based on Monte Carlo simulation. In addtion,the network structure is taken into consideration for the system reliability. Experimental results show that the relative deviation of the system- level reliability is up to 60% if the No C communication structure is discarded.

关 键 词：众核处理器 可靠性 蒙特卡洛仿真 片上网络 

分 类 号：TP302.7[自动化与计算机技术—计算机系统结构]