A Memory Efficient Belief Propagation Decoder for Polar Codes  

作　　者：SHA Jin LIU Xing WANG Zhongfeng ZENG Xiaoyang 

机构地区：[1]School of Electronic Science and Engineering,Nanjing University [2]Broadcom Corp. [3]State Key Laboratory of ASIC & System,Fudan University

出　　处：《China Communications》2015年第5期34-41,共8页中国通信（英文版）

基　　金：jointly supported by the National Nature Science Foundation of China under Grant No.61370040 and 61006018;the Fundamental Research Funds for the Central Universities;the Priority Academic Program Development of Jiangsu Higher Education Institutions;Open Project of State Key Laboratory of ASIC & System(Fudan University)12KF006

摘　　要：Polar codes have become increasingly popular recently because of their capacity achieving property.In this paper,a memory efficient stage-combined belief propagation(BP) decoder design for polar codes is presented.Firstly,we briefly reviewed the conventional BP decoding algorithm.Then a stage-combined BP decoding algorithm which combines two adjacent stages into one stage and the corresponding belief message updating rules are introduced.Based on this stage-combined decoding algorithm,a memory-efficient polar BP decoder is designed.The demonstrated decoder design achieves 50%memory and decoding latency reduction in the cost of some combinational logic complexity overhead.The proposed decoder is synthesized under TSMC 45 nm Low Power CMOS technology.It achieves 0.96 Gb/s throughput with 14.2mm^2 area when code length N=2^(16)which reduces 51.5%decoder area compared with the conventional decoder design.Polar codes have become increa- singly popular recently because of their capacity achieving property. In this paper, a memory efficient stage-combined belief prop- agation （BP） decoder design for polar codes is presented. Firstly, we briefly reviewed the conventional BP decoding algorithm. Then a stage-combined BP decoding algorithm which combines two adjacent stages into one stage and the corresponding belief message updating rules are introduced. Based on this stage-combined decoding algorithm, a memo- ry-efficient polar BP decoder is designed. The demonstrated decoder design achieves 50% memory and decoding latency reduction in the cost of some combinational logic complexity overhead. The proposed decoder is synthe- sized under TSMC 45nm Low Power CMOS technology. It achieves 0.96 Gb/s throughput with 14.2mm2 area when code length N=216 which reduces 51.5% decoder area compared with the conventional decoder design.

关 键 词：polar codes belief propagation stage-combined memory-efficient IMPLEMENTATION 

分 类 号：TN764[电子电信—电路与系统] TN911.22