一种应用于全数字锁相环的小数分频器设计  

Design of a Fractional-N Frequency Divider for ADPLL Application

作　　者：赵远新[1] 李巍[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2015年第2期148-155,167,共9页Journal of Fudan University：Natural Science

基　　金：国家自然科学基金资助项目(61176029);国家十二五预研课题资助项目(513***)

摘　　要：文章针对宽带全数字锁相环（All-Digital Phase-Locked Loop,ADPLL）架构的频率综合器设计了一种适合的宽分频范围的小数分频器.由于经典的宽分频范围的小数分频器结构在边界处会发生失效,文章在分析其他解决方案的同时,提出了利用可变延时单元进行固定相位校准的解决方法.本设计的可变分频比分频器分频比范围为32-127,输入频率为1.8-3.7GHz,面积为0.46mm×0.24mm.测试结果显示,本设计有效地解决了经典宽分频范围的小数分频器结构在边界处会发生失效的问题.A fractional-N frequency divider covering a wide range is proposed for the ADPLL based frequencysynthesizer. Due to the fact that the conventional fractionabN frequency divider can＇t operate in fractional mode atthe boundary of the divider ratio, the paper analysis the other solutions to this problem and give a new way ofphase error calibration with a delay-variable cell. The divider-ratio-variable divider has a wide range from 32 to 127in the aspect of divider ratio; the input frequency range of the divider covers 1.8 GHz to 3.7 GHz and the divideroccupies an area of 0. 46 mmX0. 24 ram. The measured result shows that the proposed architecture can effectivelysolve the problem of fractional operation failure at the boundary.

关 键 词：全数字锁相环 小数分频器 可变延时单元 

分 类 号：TN772[电子电信—电路与系统]