一种应用于全数字锁相环的时间数字转换器设计  

Design of a Time-to- Digital Converter for ADPLL Application

作　　者：高源培 李巍[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《复旦学报（自然科学版）》2015年第2期168-174,183,共8页Journal of Fudan University：Natural Science

基　　金：国家自然科学基金资助项目(61176029);国家十二五预研课题资助项目(513***)

摘　　要：设计了一个应用于全数字锁相环的时间数字转换器(TDC).该时间数字转换器具有两种工作模式——粗量化和细量化.为了提高细量化模式的测量范围,TDC采用1-bit decision-select结构和游标门控环形振荡器(Vernier GRO)构成其两级量化单元.通过在Vernier GRO中使用一种新型结构的比较器,消除了用SR触发器做比较器时对测量范围的制约,也提高了GRO设计的灵活性.在TSMC 0.13μm工艺,1.2 V电源电压和40MHz采样速率下,仿真结果表明本设计的TDC在粗量化模式下具有不小于25ns的测量范围,在细量化模式下有效分辨率和测量范围分别为30ps,1.8ns.A Time-to-Digital Converter（TDC）for All-Digital Phase-Locked LOOp（ADPLL） application is designed.The TDC has two operation modes, coarse mode and fine mode. To enlarge the detectable range of fine mode, theTDC utilizes 1-bit decision-select structure and Vernier GRO as its two-stage Quantization Unit. Using a newstructure comparator in Vernier GRO eliminates the limitation to detectable range when using SR flip-flo.p ascomparator, and also improve the design flexibility of GRO delay cell. The TDC is designed in TSMC 0. 13 μmCMOS technology. With 1.2 V power supply and 40 MHz sampling rate, simulation result shows that detectablerange of coarse mode can be 25 ns, effective resolution and detectable range of fine mode is 30 ps, 1.8 ns.Keorfls： time-to-digital converter; vernier gated-ring-oscillator; all-digital phase-locked loop

关 键 词：时间数字转换器 游标门控环形振荡器 全数字锁相环 

分 类 号：TN772[电子电信—电路与系统]