高精度模拟分频电路的设计与实现  

Design and Implementation of High-precision Analog Frequency Dividing Circuit

作　　者：王晋伟[1] 崔永俊[1] 贾磊[1] 杨兵[1] 

机构地区：[1]中北大学电子测试技术国家重点实验室和仪器科学与动态测试教育部重点实验室,太原030051

出　　处：《科学技术与工程》2015年第15期44-49,60,共7页Science Technology and Engineering

基　　金：国家自然科学基金项目(61335008)资助

摘　　要：针对精密授时系统中,铷原子钟只提供单一的10 MHz高精度信号,而用FPGA等数字分频设计精度达不到要求的问题,设计了采用电阻、电容、电感与运算放大器等简单器件构成的高精度模拟分频电路。对高精度分频电路中各个模块的设计进行了详细的描述。通过测试,设计的一分频与二分频电路都能够使精度达到±5×10-11,这比一般的数字分频器要高几个数量级。According to the problem that the rubidium-disciplined crystal oscillator provides only a single 10MHz high-precision signal in precision timing system and the accuracy of digital frequency divider is not up to the requirements designed by FPGA, a high-precision analog frequency dividing circuit consisted of simple device such as resistors, capacitors, inductors and the operational amplifiers is designed. The design of each module in high- precision frequency dividing circuits is described in detail. Through testing, the design of a divider and two divider are able to achieve accuracy ±5 ×10-11, which is several orders of magnitude higher than the average digital divi- der.

关 键 词：铷原子钟 高精度分频 模拟电路 

分 类 号：TN772[电子电信—电路与系统]