一种基于Σ-Δ调制小数分频PLL的低杂散宽带频率合成器设计  

A New Design of Low Spurious Wide Band Frequency Synthesizer Based on Σ-Δ Modulation Fractional PLL

作　　者：叶宝盛[1] 符明飞 王晓安[1] 

机构地区：[1]中国电子科技集团公司第三十六研究所,浙江嘉兴314033

出　　处：《通信对抗》2015年第1期38-41,共4页Communication Countermeasures

摘　　要：通过研究Σ-Δ小数分频PLL输出的杂散特性,提出使用不断变化的时钟参考频率可以实现宽频带频率合成器的低杂散性能。还使用了DDS作为可变参考源,克服了DDS输出频带受到限制且宽带SFDR差的缺点,且避开了小数分频因其固有鉴相频率谐波以及次谐波边带杂散性能较差的区域。实现了1.5-3GHz全频带杂散优于-80d Bc的频率合成器设计。By studying the spur properties of Σ- Δ modulated fractional PLL it is discovered that changing the reference frequency can realize lower spurious in wide band frequency synthesizer designs. In this paper we use DDS as the changing reference frequency. Not only the disadvantage of output frequency band limits and bad SFDR of DDS can be avoided, but the frequency band of poor spurious of fractional PLL can also be skipped. A frequency synthesizer of 1.5 to 3 GHz is realized and spur levels are below-80 d Bc in the whole frequency band.

关 键 词：Σ-Δ调制 DDS 小数分频PLL 宽频带频率合成器 低杂散 

分 类 号：TN74[电子电信—电路与系统]