一种用于高速锁相环的整数分频器设计  

Design of an Integer Frequency Divider for High Speed PLL

作　　者：庞遵林[1] 郭锐[1] 

机构地区：[1]中国电子科技集团第38研究所集成电路设计中心,安徽合肥230088

出　　处：《电子科技》2015年第6期104-107,共4页Electronic Science and Technology

摘　　要：根据IEEE 802.3ae XAUI协议中锁相环的设计指标,基于65 nm CMOS工艺,设计实现了一种高速可编程整数分频器。采用高性能D型触发器对压控振荡器输出时钟进行预分频,分频器由4/5双模预分频器、2 Bit和5 Bit计数器组成,可实现8~131的连续分频比。仿真结果表明,在1 V供电条件下,分频器最高工作频率可达4.375 GHz,消耗电流〈0.4 m A。A programmable high speed integer divider based on the 65 nm CMOS （ Complementary Metal Oxide Semiconductor, CMOS） technology is designed according to the specifications of the phase locked loop in the IEEE 802. 3ae XAUI protocol. A D-flip flow trigger is used to percale the output clock of voltage control oscillator, and the divider building blocks （ the 4/5 dual modulus percale and 2- and 5-bit programmable counters） are capable of operating within the division ratio of 8 - 131. Simulation results show that the maximum operating frequency of the proposed divider is 4. 375 GHz, and the current is less than 0. 4 mA at 1 V supply voltage.

关 键 词：分频器 高速 低功耗 CMOS 

分 类 号：TN432[电子电信—微电子学与固体电子学] TN911.8