基于FPGA的AXI4总线时序设计与实现  

Design and implementation of AXI 4 bus timing based on FPGA

作　　者：马飞[1] 刘琦[1] 包斌[1] 

机构地区：[1]北京空间机电研究所,北京100094

出　　处：《电子技术应用》2015年第6期13-15,19,共4页Application of Electronic Technique

摘　　要：针对AXI4总线设备之间的高速数据传输需求,根据AXI4总线协议,设计实现了一种基于FPGA的AXI4总线读写时序控制方法。以FPGA为核心,采用VHDL语言,完成了满足AXI4总线协议的读猝发方式数据传输和写猝发方式数据传输时序控制模块的设计。利用FPGA内部嵌入式系统提供的高性能数据传输接口完成AXI4时序控制模块的功能验证。实际应用表明,依据提出的设计方法实现的读写时序控制模块能够满足AXI4总线协议规定的时序关系,实现数据的高速正确传输,总线数据传输速率能够达到1.09 GB/s。To fulfill the needs for high speed data transfers between AXI 4 bus devices, a FPGA based timing control method of data writing and reading for AXI 4 bus is provided. Timing control modules of data writing and reading in burst are designed according to the AXI 4 bus protocol. Functions of the design are validated in high performance interfaces of embedded system in FPGA. The application shows that the design provided in this paper provides an accurate timing that meets the AXI 4 bus protocol. Data transports between AXI 4 bus devices correctly in the speed of 1.09 GB/s.

关 键 词：AXI4总线 时序控制 

分 类 号：TP336[自动化与计算机技术—计算机系统结构]