红外焦平面读出电路集成数字输出  

IRFPA ROIC integrated digital output

作　　者：高磊[1,2] 翟永成[1,2] 梁清华[1,2] 蒋大钊 丁瑞军[1] 

机构地区：[1]中国科学院上海技术物理研究所中国科学院红外成像材料与器件重点实验室,上海200083 [2]中国科学院大学,北京100049

出　　处：《红外与激光工程》2015年第6期1686-1691,共6页Infrared and Laser Engineering

摘　　要：为了实现红外焦平面数字化输出,设计了一种集成片上模数转换的焦平面读出电路,包括一个512×512的读出电路单元阵列和列共享的逐次逼近寄存器型模数转换器(SAR ADC)。单元读出电路采用了直接注入(DI)结构作为输入级,输出的信号通过多路传输送到模数转换器。设计的逐次逼近型的模数转换器中的比较器采用的是由前置放大器、锁存器、自偏置差分放大器和输出驱动器组成的高速比较器,数模转换器(DAC)采用的是三段式的电荷按比例缩放和电压按比例缩放相结合的结构。在Cadence和Synopsys设计平台下对模拟和数字部分电路分别进行设计、仿真与版图设计。电路工艺采用GLOBALFOUNDRIES公司0.35μm CMOS 3.3 V工艺加工流片。测试结果显示SAR ADC有效位数为8.2位,转换频率超过150 k Samples/s,功耗低于300μW,满足焦平面100帧频以及低功耗的需求。In order to achieve infrared focal plane digital output, an IRFPA readout circuit integrated on-chip ADC was designed, including a 512 ×512 cell array readout circuit and shared the successive approximation register analog to digital converters（SAR ADC）. Unit readout circuit using direct injection（DI） structure as the input stage, the output signal was sent through the multiplexes to ADC. The comparator designed in successive approximation ADC was a high-speed comparator which consisted of the preamplifier, latches, self-biasing differential amplifiers and output drives. The digital to analog converter（DAC） used a three-stage structure which the charge scaling was combined of voltage scaling.Using the Cadence and Synopsys design platform for circuit′ s design, simulation and layout design. The circuit was taped out by GLOBALFOUNDRIES company using 0.35 μm, 3.3 V CMOS process. Test results show the number of significant digits of ADC is 8.2 bit, converts frequency is 150 k Samples/s,power consumption less than 300 μW and meet the needs of focal plane 100 frame rates as well as low power consumption.

关 键 词：红外焦平面 读出电路 片上ADC SAR DAC 

分 类 号：TN21[电子电信—物理电子学]