H.264中CAVLC解码器的设计与优化  

Design and Optimization of H.264 CAVLC Decoder

作　　者：李桃中 王进祥[1] 苏阳平 祁睿[1] 

机构地区：[1]哈尔滨工业大学微电子中心,哈尔滨150001

出　　处：《微电子学》2015年第3期372-375,共4页Microelectronics

摘　　要：为了提高CAVLC解码器的解码速率,提出了一种优化的CAVLC解码器结构,主要包括level解码模块和RunBefore解码模块。level解码模块采用伪并行的结构解码幅值,实现了半个周期解码一个幅值;采用RunBefore与level快速合并的方法,在RunBefore解码完成的同时形成残差系数。建立了该优化结构的RTL模型,并验证了其功能的正确性。利用Xilinx公司的ISE13.3对该设计进行综合,结果显示该设计可以支持1 080p高清视频的实时解码。To increase the decoding rate of the CAVLC decoder, an optimized architecture of CAVLC decoder was proposed, including Level decoding module and RunBefore decoding module. Level decoding module used a false parallel architecture to decode level, so that it could decode a level in half a cycle. By employing quick combination of RunBefore and Level, residual coefficients had been formed right after the decoding of RunBefore. An optimized RTL model was set up, and it was verified and synthesized by ISE13.3. The synthesis results showed that the design could support the real-time decoding of 1080 p high definition video.

关 键 词：H.264解码器 CAVLC解码器 伪并行结构 快速合并方法 

分 类 号：TN47[电子电信—微电子学与固体电子学]