高速大容量存储电路板的信号性能分析研究  

Study on signal performance analysis of high-speed transferring and large-capacity memory circuit board

作　　者：侯斌[1] 杨祎[1] 巩稼民[1] 

机构地区：[1]西安邮电大学电子工程学院,陕西西安710121

出　　处：《现代电子技术》2015年第13期137-140,144,共5页Modern Electronics Technique

基　　金：国家高技术研究发展计划(863计划)课题项目(2013AA014504);西安邮电大学2013年研究生创新基金资助项目(ZL2013-22)

摘　　要：针对高速电路的PCB设计中拓扑结构产生的信号完整性问题,以TI8168芯片与高速多片DDR3的互联为背景,通过分析高速电路板中的总线拓扑结构,研究高速电路板的布线原理和信号完整性理论,提出一种T型与Fly-by相结合的拓扑结构和信号反射控制方法,采用Cadence软件中的Sig Xplorer软件进行仿真。结果表明,这种拓扑结构既解决了Fly-by结构中接收端信号的时延和实际布线困难的问题,又优化了T型拓扑中多片DDR3接收端端接的复杂问题,有效地消除了信号的延时和反射,从而保证了信号的完整性。Since the topology of PCB design generates signal integrity problem in high-speed transferring circuit, on the ba- sis of interconnection of TI8168 chip and high-speed multi-chip DDR3, wire arrangement principle and signal integrity theory of high-speed transferring circuit board are studied by analyzing the bus topology in high-speed transferring circuit board. Signal reflection control method and the combined topology of T-type and Fly-by are proposed. The topology is simulated by usirig SigXplorer software in Cadence. Simulation results show that the topology can solve signal delay in receiving terminal and actual wire ar- rangement difficulty in Fly-by topology, and optimize the complex problem of terminal joint in multi-chip DDR3 receiving terminal in T-type topology. Signal delay and reflection are eliminated effectively, and signal integrity is ensured.

关 键 词：信号完整性 拓扑结构 信号反射 端接 时延 

分 类 号：TN802.34[电子电信—信息与通信工程]