多核处理器的功耗估算模型  

Power Estimation Model on Multi-Core Platforms

作　　者：刘辛[1] 沈立[1] 苏博 王志英[1] 

机构地区：[1]高性能计算国家重点实验室(国防科学技术大学计算机学院),湖南长沙410073

出　　处：《软件学报》2015年第7期1840-1852,共13页Journal of Software

基　　金：国家高技术研究发展计划(863)(2012AA010905);国家自然科学基金(61472431;61272143)

摘　　要：精确的功耗估算能够为操作系统调度、软/硬件能效优化提供有效的指导.以往的研究表明:通过监测处理器内部相关硬件事件(如提交的指令数、Cache访问次数等),可以对功耗进行估算.但是,已有的相关功耗模型的精度并不理想,误差通常在5%以上.通过分析处理器提供的硬件事件,并在众多事件中筛选出一组与程序运行功耗密切相关的事件,使用逐步多元线性回归分析,建立了一个与应用无关的实时功耗估算模型,该模型可以直接移植到支持SMT的平台上.通过PARSEC和SPLASH2两个基准测试程序集进行了验证,估算误差分别为3.01%和1.99%.针对建模耗时长的问题,提出了基于两阶聚类的优化改进方法.所提出的估算模型能为构建具有动态平衡功耗和平滑峰值功耗的智能功耗感知系统提供借鉴.Accurate power consumption estimation can provide a significant guidance for OS scheduling and software/hardware power efficiency optimization. Previous researches have indicated that power consumption can be estimated by monitoring the related hardware events inside the CPU, such as instruction submission times and caches access times. However, those models which are based on hardware are not able to provide accurate results; they often come with an error over 5%. This study first analyzes the hardware events provided by the CPU, then chooses a set of events that are closely related to power consumption, and finally uses step by step multi-element linear regression analysis to build our run-time estimation model. This model is not related to any applications and can be directly transformed into the platforms that support SMT. The model is verified with the two benchmark suites PARSEC and SPLASH2, resulting in estimated errors of 3.01% and 1.99% respectively. To address the issue of high time consuming in modeling, an optimization scheme with two-step cluster is also presented in this article. The proposed estimation model can serve as a foundation for the intelligent power consumption perception systems that dynamically balance power assignment and smooth peak power consumption at run-time.

关 键 词：功耗估算 性能计数器 多核 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]