基于FPGA的全数字化峰值时刻检测技术  

Full digital peak time discrimination technique based on FPGA

作　　者：王飞[1] 

机构地区：[1]激光与物质相互作用国家重点实验室,中国科学院长春光学精密机械与物理研究所,长春130033

出　　处：《电子测量与仪器学报》2015年第6期914-919,共6页Journal of Electronic Measurement and Instrumentation

基　　金：国家863计划(2013AAxxx1024G)资助项目

摘　　要：基于阈值的前沿到达时刻判别方法受信号幅度变化的影响较大,通常具有较大的随机游走。更为精确的恒比定时等方法需要额外的硬件,会提高系统的复杂度。为解决这一难题提出了利用FPGA实现的全数字化峰值时刻检测技术。首先由时间测量理论角度出发,分析了信号幅度变化引起随机游走的原因,并针对具有一定前后沿对称性的信号研究了利用信号前后沿计算峰值时刻的理论依据。随后利用FPGA对此技术进行了硬件实现,并搭建了测试平台,对测量结果进行了实验测试。对25 ns脉冲信号的测试结果表明,采用全数字化峰值时刻检测技术后,系统的时间的随机游走由5 ns提高到0.24 ns以内。Threshold method based leading edge discrimination suffers higher timing random walk introduced by am- plitude variation. More precise constant fraction discrimination method needs special hardware which could increase the system complexity. In order to solve this problem, a FPGA based full digital peak time discrimination technique is introduced. First, the theory of amplitude caused time random walk is analyzed. A theoretical base is founded for signals with some degree of symmetry with the leading edge and trailing edge. Then this technique is implemented in FPGA, and the testing system is setup to evaluate the validness of this method. For signal with 25 ns of pulse width, the random walk can be reduced from 5 ns to within 0.24 ns with the introduced full digital peak time dis- crimination technique.

关 键 词：时间间隔测量 峰值时刻检测 抽头延迟线 时间数字转换 

分 类 号：TN247[电子电信—物理电子学]