基于MATLAB的全数字锁相环的设计与实现  

Design and Implementation of All Digital Phase-locked Loop Based on MATLAB

作　　者：侯永飞[1] 倪永婧[2] 王全喜[1] 

机构地区：[1]中国电子科技集团公司第五十四研究所,河北石家庄050081 [2]河北科技大学,河北石家庄050000

出　　处：《无线电工程》2015年第7期79-82,共4页Radio Engineering

摘　　要：由于锁相环工作频率高,对其进行仿真,数据量大,仿真时间长。为了提高锁相环设计效率,有必要建立一个高效的仿真模型。详细分析了全数字锁相环的构成及各个模块的工作原理,在理论分析的基础上建立了全数字锁相环的数字模型,并用MATLAB语言构建了一种新的全数字锁相环仿真模型。仿真验证了这种全数字锁相环实现的可行性,仿真结果与理论分析基本一致。Due to the high operation frequency of PLL,the PLL simulation features large data amount and long simulation duration. Therefore,in order to improve the efficiency of PLL design,it is necessary to establish an efficient model for PLL design. In this thesis,the structure of ADPLLand the principle of each module are described in detail. A mathematical modelon ADPLL is established on the basis of theoretical analysis. Based on previous models for PLL,a new behavioral model for all-digital PLL in MATLAB environment is presented. The simulation test proves the feasibility of the ADPLL. The resultsmainly accord with the theoretical analysis.

关 键 词：全数字锁相环 数字环路滤波器 数控振荡器 MATLAB 

分 类 号：TN911.8[电子电信—通信与信息系统]