时延约束下快速门级双电压分配算法  

Fast gate level dual-voltage assignment algorithm under timing constraints

作　　者：涂凤娥 夏银水[1] 储著飞[1] 王伦耀[1] 

机构地区：[1]宁波大学信息科学与工程学院,浙江宁波315211

出　　处：《计算机工程与应用》2015年第11期201-205,共5页Computer Engineering and Applications

基　　金：国家自然科学基金重点项目(No.61131001);教育部博士点基金(No.20113305110001);宁波市自然科学基金(No.2013A610003);浙江省教育厅科研项目(No.Y201016754)

摘　　要：针对门级电压分配算法速度慢的问题,提出了一种时延约束下基于门分组的双电压分配算法。通过门工作在低、高电压下的延时差与时延裕量的比较,将门分为高电压门组和低电压门组;针对违反时延约束的关键路径上的低电压门(称为关键低电压门),采用最小割法逐渐升高其电压至电路满足时延约束。通过对ISCAS’85标准电路测试的实验结果表明,与已发表的算法比较,不但功耗有一定改进,且算法速度快。Against the low speed of gate-level voltage assignment algorithm, a gate grouping based dual-voltage assignment algorithm under timing constraint is proposed. Through comparing gate delay difference working under low and high voltage and its slack, all gates are classified into high voltage gate group and low voltage gate group. Against so-called critical low voltage gates violating timing constraint on critical paths, the min-cut method is employed to gradually increase the applied voltage until the circuit meets timing constraint. The experimental results on ISCAS＇85 benchmarks indicate that compared with the published algorithms, the proposed algorithm not only can reduce power dissipation, but also can improve algorithm speed.

关 键 词：分组 最小割 时延裕量 双电压分配 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]