嵌入式微处理器中的低功耗Cache技术研究  

Research on Low Power Consumption Cache Technology in Embedded Microprocessor

作　　者：胡瑞 马鹏 章建雄 

机构地区：[1]中国电子集团公司第三十二研究所,上海200233

出　　处：《计算机工程》2015年第7期75-81,共7页Computer Engineering

摘　　要：高速缓冲存储器(Cache)作为微处理器的重要组成部分,在芯片面积和功耗上都占比过高。针对Cache功耗问题,基于分段访问Cache技术和路预测Cache技术,提出一种低功耗组相联Cache的预访问策略。在Cache中增加一个缓冲寄存器(Buffer),用以存储最近Cache命中后被访问的标签和数据子阵列信息。在开始进行标签访问之前,选中该Buffer,并将所访问的Cache标签和Buffer标签进行匹配,根据匹配结果选择采用路预测访问或分段访问方式。通过Mi Bench基准测试程序并使用Simple Scalar和Sim-Panalyzer进行实验,结果表明,与传统组相联Cache技术相比,该策略能降低25.15%的能量延迟积。Cache,as an important part of the microprocessor, accounts for an undueproportion of the chip area and power consumption, which is a problem needs to be solved, especially the intensiveenergy cost. Under the background and based on two kinds of micro structural-level low-power optimization techniques for set-associative Cache phased Cache, as well as the way-predicting one, this paper proposes a low-power set-associative pre-access Cache strategy. In this strategy, Buffer is added in Cache to store the hit tag and data subarray-information from hit Cache. It selects the buffer before accessing the tag, and then matches the tag from two parts accessed Cache and Buffer. Referring to the matching result, way-predicting or phased Cache can be chosen to access. Experimental results through MiBench benchmarks, Simple-Scalar and Sim-Panalyzer show that Energy-delay Product （ EDP ） can be reduced by 25. 15% in this strategy.

关 键 词：低功耗 高速缓冲存储器 多路组相联 路预测 分阶段 预访问 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]