数模混合高速集成电路封装基板协同设计与验证  

Package Substrate Co-Design and Validation of the High-Speed Digital-Analog Mixed Signal IC

作　　者：陈珊[1] 蔡坚[1,2] 王谦[1] 陈瑜[1] 邓智[3] 

机构地区：[1]清华大学微电子学研究所,北京100084 [2]清华信息科学与技术国家实验室(筹),北京100084 [3]清华大学工程物理系,北京100084

出　　处：《半导体技术》2015年第7期542-546,共5页Semiconductor Technology

基　　金：国家科技重大专项(2013ZX02502)

摘　　要：介绍了数模混合高速集成电路(IC)封装的特性以及该类封装协同设计的一般分析方法。合理有效的基板设计是实现可靠封装的重要保障,基于物理互连设计与电设计协同开展的思路,采用Cadence APD工具以及三维电磁场仿真工具实现了特定数模混合高速集成电路(一款探测器读出电路)的封装设计与仿真论证,芯片封装后组装测试,探测器系统性能良好,封装设计达到预期目标。封装电仿真主要包含:封装信号传输通道S参数提取、电源/地网络评估,探测器读出芯片封装体互连通道设计能满足信号带宽为350 MHz(或者信号上升时间大于1 ns)的高速信号的传输。封装基板布线设计与基板电设计协同分析是提高数模混合高速集成电路封装设计效率的有效途径。The characteristics of the high-speed digital-analog mixed signal integrated circuit（ IC）packages were presented,and the general method of its co-design was introduced. The reliable packaging performance highly depends on an effective substrate design. Based on the synergetic design,Cadence APD and 3D finite element electromagnetic simulation software were applied to realize the design and simulation verification of a particular dedicated high-speed mixed signal IC（ read-out chip of one detector）package. The detector system board was tested after assembling the package and the testing system works well,indicating the favorable package performance of the read-out chip. The electrical simulation of the packaging substrate mainly includes the extraction of signal channel S parameters and evaluation of power / ground network. The good system performance was obtained through electrical testing,which means the package interconnection design realizes the reliability transmission of high-speed signal. The band width of high-speed signal is 350 MHz,or its rise time is no smaller than 1 ns. The results show that the coordination of packaging substrate routing design and the electrical design are the superior way to improve efficiency of high-speed digital-analog mixed signal packaging design.

关 键 词：数模混合高速集成电路(IC) 封装基板协同设计 封装基板电仿真 S参数 直流压降 

分 类 号：TN405[电子电信—微电子学与固体电子学]