面向MPSoC性能评估的高速缓存建模技术  

Cache modeling for MPSoC performance estimation

作　　者：修思文[1] 李彦哲[1] 黄凯[1] 马德[2] 晏荣杰[3] 严晓浪[1] 

机构地区：[1]浙江大学超大规模集成电路研究所,浙江杭州310027 [2]杭州电子科技大学微电子CAD所,浙江杭州310018 [3]中国科学院软件研究所,北京100080

出　　处：《浙江大学学报（工学版）》2015年第7期1367-1375,共9页Journal of Zhejiang University：Engineering Science

基　　金：中央高校基本科研业务费专项资金资助项目(2013QNA5008);国家科技重大专项基金资助项目(2009ZX01030-001-002);国家自然科学基金资助项目(61100074)

摘　　要：分析现有的面向MPSoC性能评估的高速缓存建模技术的缺点,提出用于本机模拟的静态分析和动态标注相结合的缓存建模技术.该技术采用GCC剖析,避免了命中判断时标签比较,扩展了缓存更新的粒度.建立准确的指令和各类型变量在目标平台的地址映射表,提高了仿真速度和评估的准确性.该技术支持对多级缓存的建模,扩展了对多处理器平台的支持.实验结果表明,该技术的评估速度和准确性均优于现有技术.The disadvantages of existing cache modeling techniques for MPSoC performance estimation were analyzed.An static analysis and dynamic annotation combined cache modeling technique for native simulation was proposed.The technique employs GCC profiling,avoids tag-search for hit/miss judgment,and coarsens the granularity of cache updating.An accurate address mapping table for instruction and all types of data variables was established,which improves both simulation speed and estimation accuracy.Multilevel cache modeling was considered,which extends support for multi-processor platform.Experimental results show that the proposed technique can significantly reduce the simulation time and improve the accuracy of estimation result compared with existing techniques.

关 键 词：MPSoC性能评估 高速缓存建模 本机模拟 GCC剖析 静态分析 动态标注 多级缓存 

分 类 号：TN47[电子电信—微电子学与固体电子学]