An efficient method for comprehensive modeling and parasitic extraction of cylindrical through-silicon vias in 3D ICs  

作　　者：姚蔷 叶佐昌 喻文健 

机构地区：[1]Institute of Microelectronics, Tsinghua University [2]Department of Computer Science and Technology, Tsinghua University

出　　处：《Journal of Semiconductors》2015年第8期150-156,共7页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(No.61422402);the Tsinghua University Initiative Scientific Research Program

摘　　要：To build an accurate electric model for through-silicon vias （TSVs） in 3D integrated circuits （ICs）, a resistance and capacitance （RC） circuit model and related efficient extraction technique are proposed. The circuit model takes both semiconductor and electrostatic effects into account, and is valid for low and medium signal frequencies. The electrostatic capacitances are extracted with a floating random walk based algorithm, and are then combined with the voltage-dependent semiconductor capacitances to form the equivalent circuit. Compared with the method used in Synopsys＇s Sdevice, which completely simulates the electro/semiconductor effects, the proposed method is more efficient and is able to handle the general TSV layout as well. For several TSV structures, the experimental results validate the accuracy of the proposed method for the frequency range from l0 kHz to 1 GHz. The proposed method demonstrated 47× speedup over the Sdevice for the largest 9-TSV case.To build an accurate electric model for through-silicon vias （TSVs） in 3D integrated circuits （ICs）, a resistance and capacitance （RC） circuit model and related efficient extraction technique are proposed. The circuit model takes both semiconductor and electrostatic effects into account, and is valid for low and medium signal frequencies. The electrostatic capacitances are extracted with a floating random walk based algorithm, and are then combined with the voltage-dependent semiconductor capacitances to form the equivalent circuit. Compared with the method used in Synopsys＇s Sdevice, which completely simulates the electro/semiconductor effects, the proposed method is more efficient and is able to handle the general TSV layout as well. For several TSV structures, the experimental results validate the accuracy of the proposed method for the frequency range from l0 kHz to 1 GHz. The proposed method demonstrated 47× speedup over the Sdevice for the largest 9-TSV case.

关 键 词：3D IC through silicon via （TSV） parasitic extraction floating random walk algorithm metal-oxide- semiconductor （MOS） capacitance 

分 类 号：TN401[电子电信—微电子学与固体电子学]