A 10-bit 120-MS/s pipelined ADC with improved switch and layout scaling strategy  

作　　者：周佳 许丽丽 李福乐 王志华 

机构地区：[1]Institute of Microelectronics, Tsinghua University [2]Tsinghua National Laboratory for Information Science and Technology, Tsinghua University

出　　处：《Journal of Semiconductors》2015年第8期166-170,共5页半导体学报（英文版）

摘　　要：A 10 bit, 120 MS/s two-channel pipelined analog-to digital converter （ADC） is presented. The ADC is featured with improved switch by using the body effect to improve its conduction performance. A scaling down strategy is proposed to get more efficiency in the OTA＇s layout design. Implemented in a 0.18-μm CMOS technol- ogy, the ADC＇s prototype occupied an area of 2.05 × 1.83 mm2. With a sampling rate of 120-MS/s and an input of 4.9 MHz, the ADC achieves a spurious-free-dynamic range of 74.32 dB and signal-to-noise-and-distortion ratio of 55.34 dB, while consuming 220-mW/channel at 3-V supply.A 10 bit, 120 MS/s two-channel pipelined analog-to digital converter （ADC） is presented. The ADC is featured with improved switch by using the body effect to improve its conduction performance. A scaling down strategy is proposed to get more efficiency in the OTA＇s layout design. Implemented in a 0.18-μm CMOS technol- ogy, the ADC＇s prototype occupied an area of 2.05 × 1.83 mm2. With a sampling rate of 120-MS/s and an input of 4.9 MHz, the ADC achieves a spurious-free-dynamic range of 74.32 dB and signal-to-noise-and-distortion ratio of 55.34 dB, while consuming 220-mW/channel at 3-V supply.

关 键 词：ADC PIPELINE body-effect scaling down parallel 

分 类 号：TN792[电子电信—电路与系统] TM564[电气工程—电器]