一种低抖动电荷泵锁相环的设计  

Design of a Low- Jitter Charge Pump Phase-Locked Loop

作　　者：白杨[1] 张万荣 江之韵[1] 胡瑞心[1] 卓汇涵[1] 陈昌麟[1] 赵飞义 

机构地区：[1]北京工业大学电子信息与控制工程学院,北京100124

出　　处：《电子器件》2015年第3期516-520,共5页Chinese Journal of Electron Devices

基　　金：北京市自然基金项目(4142007;4143059)

摘　　要：采用动态鉴频鉴相器、基于常数跨导轨到轨运算放大器的电荷泵、差分型环形压控振荡器,设计了一种低抖动的电荷泵锁相环。基于SMIC 0.18-μm CMOS工艺,利用Cadence软件完成了电路的设计与仿真。结果表明,动态的鉴频鉴相器,有效消除了死区。新型的电荷泵结构,在输出电压为0.5 V^1.5 V时将电流失配减小到了2%以下。压控振荡器在频率为1 MHz时输出的相位噪声为-94.87 d B在1 MHz,调谐范围为0.8 GHz^1.8 GHz。锁相环锁定后输出电压波动为2.45 m V,输出时钟的峰峰值抖动为12.5 ps。A low-jitter charge pump phase-locked loop（ CPPLL） was proposed to resolve the problems of jitter of conventional CPPLL. The CPPLL consists of a dynamic phase frequency detector,a charge pump based on constantgm rail-to-rail operational amplifier,a differential ring VCO. Based on SMIC 0. 18-μm CMOS process,the novel CPPLL was designed and verified by Cadence. The results indicated the dynamic PFD effectively eliminated the dead zone to reduce the jitter of CPPLL. The current mismatch of novel CP was less than 2% when the output voltage ranged from 0. 5 V to 1. 5 V. The output phase noise of VCO was- 94. 87 d B at 1 MHz when the frequency was 1 MHz. The tuning range of VCO was 0. 8 GHz ~ 1. 8 GHz. Output voltage fluctuation of locking CPPLL was2. 45 m V. Peak-peak jitter of output clock was 12. 5 ps.

关 键 词：电荷泵锁相环 低抖动 常数跨导轨到轨运算放大器 环形压控振荡器 

分 类 号：TN433[电子电信—微电子学与固体电子学]