一种基于FLASH的混合式11位ADC设计  

Design of Low-Power 11-bit ADC Based on the Hybrid Architecture

作　　者：田德永 黄维超[2] 

机构地区：[1]贵州职业技术学院,贵阳550000 [2]贵州大学大数据与信息工程学院,贵阳550025

出　　处：《电子器件》2015年第3期562-568,共7页Chinese Journal of Electron Devices

基　　金：贵州省教育厅自然科学研究项目(黔教合KY字(2013)193)

摘　　要：时域延迟线架构ADC的非线性问题,导致其无法达到较高的分辨率。针对该问题,提出了一种将Flash和延迟线架构相结合的新型低功耗11位ADC。该新型混合ADC架构由两个模块构成,分别为4位Flash ADC架构和7位延迟线ADC架构,因此同时具有Flash ADC和延迟线ADC的准确性和高效性。采用CHARTERED 65 nm Dual Gate Mixed Signal CMOS Process设计并绘制出混合式ADC版图。实验测试结果显示,在供应电压为1.1 V和采样效率为100 Msample/s的条件下,混合式ADC产生的信噪失真比(SNDR)为60 d B,消耗功率为1.6 m W。在无需任何校准技术的情况下,混合式ADC产生的品质因数(FOM)为19.4 f J/分级转换。此外,利用不匹配的3σ设备进行了蒙特卡罗试验,结果表明,SNDR值低于其ADC架构。This paper presents a new type of low power 11-bit ADC based on Flash architecture and delay line architecture. The new hybrid ADC architecture is composed of two modules,respectively is 4 bit Flash ADC framework and7 delay line ADC architecture,therefore also has the accuracy of Flash ADC and efficiency of the delay line ADC. In order to reduce power the first phase of Flash ADC,the energy saving technology will DC tail current preamplifier by biasing the DC tail current of the preamplifiers at 5 μA instead of the operational current,47 μA（ in stand-by mode）.Through the use of industrial 65 nm technology,design and Simulation of a hybrid ADC is proposed in this paper. The simulation results show that,with 1. 1 V supply and 100 Msample / s,hybrid ADC signal-to-noise distortion ratio（ SNDR） is 60 d B,the power consumption is 1. 6 m W. Without any calibration technique,the quality factor of hybrid ADC generation（ FOM） into 19. 4 f J / classification. In addition,this paper uses the Monte Carlo simulation test,using the 3 device does not match the results show that,SNDR value is lower than the ADC architecture.

关 键 词：混合式ADC 延迟线架构 FLASH 加减器 

分 类 号：TN43[电子电信—微电子学与固体电子学]