一种3.3V低电源电压的1553B总线收发器设计  

Design of a 3.3V Low Supply Voltage 1553B Bus Transceiver

作　　者：印琴 于宗光[1,2] 魏敬和[1,2] 胡水根[2] 

机构地区：[1]江南大学物联网工程学院,江苏无锡214122 [2]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《电子器件》2015年第3期646-649,共4页Chinese Journal of Electron Devices

基　　金：江苏省333工程科研项目(BRA2011115)

摘　　要：提出了一种基于1553B总线的收发器系统结构,设计实现了低压单电源供电的1553B总线收发器,有效降低了收发器的动态功耗。仿真及测试结果表明,该电路能在3.3 V的低电压下实现所有的收发功能,总线占空比为100%时的最大动态功耗仅为0.5 W,相比于5 V供电的1553B总线收发器,其动态功耗大约下降了1.7 W。该收发器采用0.5μm DPTM BCD(15 V)工艺流片,并已成功应用到低压的1553B总线产品中。A system structure of bus transceiver based on 1553 B bus is presented,and a 3. 3 V low supply voltage1553 B bus transceiver which dynamic power dissipation is decreased effectively is designed. The simulation and test results show that all the transmitting and receiving function of this bus transceiver are realized with 3. 3 V supply voltage. The maximum dynamic power dissipation of 100% duty transmitter cycle is 0. 5 W,which declines 1. 7 W compared to the 5 V supply voltage 1553 B bus transceiver. The chip is fabricated at 0. 5 μm DPTM BCD（ 15 V）CMOS processes,and is adopted in low supply voltage 1553 B bus product.

关 键 词：收发器 低功耗 低压供电 1553B总线 

分 类 号：TN492[电子电信—微电子学与固体电子学]