双域可重构CIOS模乘器的研究与设计  

Research and Design of Double Domain Reconfigurable CIOS Modular Multiplier

作　　者：王威[1] 严迎建[1] 李伟[1,2] 李默然[1] 

机构地区：[1]解放军信息工程大学,郑州450001 [2]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《微电子学》2015年第4期502-506,共5页Microelectronics

基　　金：国家自然科学基金资助项目(61404175)

摘　　要：为提高ECC处理器中模乘的运算速度,并支持长度可重构的双域（素域和二元域）模乘计算,分析了CIOS模乘算法的并行性,提出了适用于硬件并行加速的双参数CIOS算法,设计了6级流水线以及多字数据并行运算的模乘硬件电路,可实现1 152位以内任意长度的双域模乘运算。在CMOS 0.18μm工艺库下综合并布局布线,电路最大时钟频率为238MHz。与其他文献的运算时间相比,160~1 024位模乘运算时间减少了17%~40%。To improve the speed of modular multiplication operation on ECC processor and support the length scalable and dual-domain （prime field and binary fields） modular multiplication, the parallelism of CIOS modular multiplication algorithm was analysed, and two-parameter CIOS algorithm suitable for hardware implementation was proposed. This multiplier exploited multi-word parallel calculation with six pipelines, which could realize dual- domain and length scalable multiplication within 1 152 bit. Implemented in CMOS 0.18μm technology, the circuit＇ s maximum clock frequency was 238 MHz. Compared to other literatures, the computation time of 160 - 1 024 bit was reduced, ranging from 17% to 40%.

关 键 词：ECC处理器 CIOS模乘算法 并行计算 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]