一种基于线性增强TDC的ADPLL设计  

Design of an All-Digital Phase-Locked Loop Based on TDC with Linear Enhancement Algorithm

作　　者：徐洪闪 甘武兵 甄少伟[1] 尤帅[1] 张波[1] 

机构地区：[1]电子科技大学电子薄膜与集成器件国家重点实验室,成都610054

出　　处：《微电子学》2015年第4期507-511,共5页Microelectronics

基　　金：博士点专项科研基金资助项目(20120185110005)

摘　　要：锁相环作为片内高速时钟的提供者,在现代电路中至关重要。提出了一种全数字锁相环的设计方案,输出频率为250 MHz,锁定时间为2μs,峰峰抖动为76ps,与传统锁相环相比,具有面积小、功耗低、可移植性好、抗干扰能力强等优点。时间数字转换器(TDC)是全数字锁相环的重要组成部分,采用线性增强算法后,与现有TDC相比,具有动态范围大、分辨率高等特点,且大大减小了积分非线性。Phase-locked loop is essential as internal high-speed clock provider in modern circuit. An all-digital phase-locked Ioop（ADPLL） was proposed with an output frequency of 250 MHz, a lock time of 2 μs and a peak- peak jitter of 76 ps. Compared with the traditional phase-locked loop, the proposed ADPLL had the advantages of small size, low power consumption, good portability and strong anti-interference capability. Time-to-digital converter （TDC） is an important component of ADPLL. TDC with the linear enhancement algorithm featured large dynamic range and high resolution, which could reduce its integral nonlinearity greatly.

关 键 词：鉴相器 线性增强算法 时间数字转换器 数字滤波器 数控振荡器 

分 类 号：TN432[电子电信—微电子学与固体电子学]