深亚微米SOC电源网络设计与优化  

The Design and Optimization for Deep Submicron SOC Power Mesh

作　　者：王成龙[1] 张万荣 林平分[1] 万培元[1] 祝雪菲 

机构地区：[1]北京工业大学电子信息与控制工程学院,北京100124

出　　处：《固体电子学研究与进展》2015年第2期171-175,共5页Research & Progress of SSE

基　　金：国家自然科学基金资助项目(60776051;61006044;61006059);北京市自然基金资助项目(4142007;4143059);北京市科技计划项目(Z141100006014032);北京市教委科技发展计划项目(KM200910005001);北京市优秀跨世纪人才基金资助项目(67002013200301)

摘　　要：针对传统电源网络设计对芯片会产生大量冗余的情况,提出一种采取模块限定布局确定优化范围,应用电源网络线宽优化释放绕线空间的非均匀阶梯型电源网络。与传统相比,此方法不但可以有效减小芯片面积与信号线总长度,而且对芯片功耗也具有优化作用。基于SMIC 0.18μm Eflash 1P4M工艺,采用Synopsys IC Compiler完成设计。芯片经流片验证,优化后版图面积减小8.69%,功耗降低4.04%。这种适用性广泛优化设计方法对电源网络设计具有一定参考价值。To reduce the amount of redundancy caused by the traditional design of power mesh for SOC,a non-uniform ladder type power mesh was proposed in this paper by limiting module place to make sure of the optimized area and optimizing line width to release the routing space.This method could not only effectively reduce the chip area and total length of signal line,but also optimize the power consumption.Based on SMIC 0.18 Eflash 1P4Mprocess,the chip′s circuit and layout were designed using Synopsys IC Compiler.After the tape-out and the test,the results show that the chip area reduces by 8.69% and power consumption reduces by 4.04%.This optimized method has some reference for the power mesh design.

关 键 词：电源网络 面积优化 功耗优化 物理设计 

分 类 号：TN492[电子电信—微电子学与固体电子学]