高压LDMOS击穿电压退化机理研究  

The Study of BVDegradation Mechanism for Ultra High Voltage LDMOS

作　　者：金锋[1,2] 徐向明[1,2] 宁开明 钱文生 王惠惠 邓彤 王鹏飞[1] 张卫[1] 

机构地区：[1]专用集成电路与系统国家重点实验室,复旦大学,上海200433 [2]上海华虹宏力半导体制造有限公司,上海201206

出　　处：《固体电子学研究与进展》2015年第4期371-376,共6页Research & Progress of SSE

摘　　要：以700V超高压LDMOS器件为例,对击穿电压的退化机理进行了物理解析及失效机理的理论分析,发现栅致漏极漏电(Gate induced drain leakage,GIDL)应力会诱导击穿电压退化,提出了多晶硅栅下场氧鸟嘴处电场强度是影响LDMOS击穿电压可靠性的重要因素。通过TCAD仿真进行确认,提出器件在版图和工艺方面的优化方案,最终通过流片验证了失效机理的正确性。硅片级和封装级的可靠性评估结果显示,优化后的器件击穿电压退化的问题得到解决并满足应用的要求。An investigation of BV degradation mechanism was presented by studying 700 V LDMOS,which proved to be induced by GIDL（Gate Induced Drain Leakage）stress.Experiment results showed that electric field intensity located at birds-beak of field oxide under the gate is the major reason to cause BV degradation.Based on the understanding of the mechanism,an optimized design of ultra high voltage LDMOS device is proposed and verified.With the newly fabricated chip,it is shown that BVdegradation problem has been solved and the device can pass both wafer-level and package-level reliability qualification after optimization.

关 键 词：高压横向扩散金属氧化物半导体 击穿电压退化 栅致漏极漏电 可靠性 

分 类 号：TN386.1[电子电信—物理电子学]