面向802.11ac的安全加速引擎Gbps VLSI架构设计与实现  

Design and implementation of Gbps VLSI architecture of the cipher engine orienting to IEEE 802.11ac

作　　者：潘志鹏[1] 吴斌[1] 尉志伟[1] 叶甜春[1] 

机构地区：[1]中国科学院微电子研究所专用集成电路与系统研究室,北京100029

出　　处：《哈尔滨工程大学学报》2015年第7期943-948,共6页Journal of Harbin Engineering University

基　　金：国家重大科技专项资助项目(2012ZX03004004)

摘　　要：针对IEEE 802.11i协议中多种安全协议实现进行研究,结合以IEEE 802.11ac协议为代表的下一代无线局域网(WLAN)系统对高吞吐率的需求,提出了一种支持WEP/TKIP/CCMP协议的多模、高速安全加速引擎的大规模集成电路(VLSI)架构。提出了基于哈希算法的密钥信息查找算法,缩小了查找时钟延迟。基于复合域的运算方式实现高级加密标准(AES)算法,提出双AES运算核的并行架构实现计数器与密码分组链接(CCM)模式,提升运算吞吐率的同时也降低了引擎的响应延迟。经过FPGA实现和ASIC流片验证表明,该安全加速引擎具备可重构性,处理延迟仅为33个时钟周期,在322 MHz工作频率下运算吞吐率可达3.747 Gbit/s。In this paper,the implementation of multiple security protocols for IEEE 802.11 i was researched. A very large scale integration（ VLSI） architecture of the multi-mode cipher engine supporting WEP / TKIP / CCMP protocols was presented taking into account the demand for high throughput of the next generation wireless local area network（ WLAN） system that is represented by IEEE 802.11 ac. A key searching algorithm based on Hash scheme was proposed to reduce the lookup clock latency. For the high throughput hardware implementation of advanced encryption standard（ AES） algorithm,composite field arithmetic was employed. In order to improve the data throughput and reduce the response time,dual AES computing core with parallel structure was used to implement the cipher block chaining message authentication code（ CCM） mode. The proposed design was implemented in both FPGA and ASIC. The results show that the cipher engine with reconfiguration architecture can achieve 33 clock cycles,and the computing throughput is 3.747 Gbit / s when the work frequency is 322 MHz.

关 键 词：安全加速引擎 多模式 密钥查找 哈希算法 AES算法 响应延迟 吞吐率 

分 类 号：TN47[电子电信—微电子学与固体电子学]