基于众核平台的CLCG并行化设计与实现  

Design and implementation of CLCG parallelization based on many integrated core

作　　者：杨杰[1] 宋博文[2,3] 张保东[2,3] 周晓辉[2,3] 

机构地区：[1]西安邮电大学国有资产管理处,陕西西安710121 [2]西安邮电大学计算机学院,陕西西安710121 [3]高效能服务器和存储技术国家重点实验室,山东济南251621

出　　处：《西安邮电大学学报》2015年第4期66-69,73,共5页Journal of Xi’an University of Posts and Telecommunications

基　　金：高效能服务器和存储技术国家重点实验室开放基金资助项目(2014HSSA13);陕西省自然科学基础研究计划资助项目(2013JM8028)

摘　　要：针对组合式线性同余产生器,在众核平台上给出一种并行化设计。该设计依据组合式线性同余产生器串行算法原理,将组合式线性同余产生器周期内的随机数序列进行分块产生,每个线程独立产生一段周期内的随机数子序列,从而进行并行化处理。实验结果表明,该设计能够通过TestU01的452项测试,移植到Intel MIC平台后性能良好,产生10 000 000 000个随机数的时间相对CPU单线程的最优加速比为14.61。The way to implement the parallelization of Random number generator CLCG based on Many Integrated Core （MIC） is discussed in this paper. By taking advantage of the parallelization of algorithm and by means of partitioned generating random number sequence of one cycle, random number sequences of one cycle is generated by each thread independently, and therefore parallelization is achieved. Experimental results show that the parallelized CLCG generator can successfully pass 452 tests of TestU01. The results is same as that of CLCG generator without parallelized. The speedup based on the MIC is very impressive, and the best speedup of the time which generating 10 000 000 000 random numbers can reach 14.61 relative to single-thread with the CPU.

关 键 词：随机数产生器 并行化 组合式线性同余产生器 集成众核 TestU01 

分 类 号：TP311.52[自动化与计算机技术—计算机软件与理论]