12 bit 200 MS/s时间交织流水线A/D转换器的设计  

Design of a 12 bit 200 MS/s Time-Interleave Pipelined A/D Converter

作　　者：杨阳[1] 张科峰[1] 任志雄[1] 刘览琦[1] 

机构地区：[1]华中科技大学光学与电子信息学院,武汉430073

出　　处：《半导体技术》2015年第9期647-652,662,共7页Semiconductor Technology

基　　金：国家科技重大专项资助项目(2010ZX03007-002-02)

摘　　要：介绍了一款应用于无线收发系统的12 bit 200 MS/s的A/D转换器(ADC)。流水线型模数转换器是从中频采样到高频采样并且具有高精度的典型结构,多个流水线型模数转换器利用时间交织技术合并成一个模数转换器的构想则是复杂结构和能量利用率之间的折中选择。采用了时间交织、流水线和运算放大器共享等技术,既提高了速度和精度,也节省了功耗。同时为了减小时序失配对时间交织流水线ADC性能的影响,提出了一种对时序扭曲不敏感的采样保持电路。采用SMIC0.13μm CMOS工艺进行了电路设计,核心电路面积为1.6 mm×1.3 mm。测试结果表明,在采样速率为200 MS/s、模拟输入信号频率为1 MHz时,无杂散动态范围(SFDR)可以达到67.8 d B,信噪失真比(SNDR)为55.7 d B,ADC的品质因子(Fo M)为1.07 p J/conv.,而功耗为107 m W。A 12 bit 200 MS / s analog-to-digital converter（ ADC） for wireless transceiver was introduced. A pipelined ADC architecture was a typical ADC structure with high resolution,which operated at medium to high sampling rate. Several pipelined ADCs using the time-interleave technique for the entire ADC were suggested. The time-interleave entire pipelined ADC also causes complex architecture and has energy efficiency. The time-interleave,pipeline and operation amplifier sharing techniques were adopted to obtain high-speed,high-resolution and reduce power consumption. Moreover,in order to reduce the influences of the timing-mismatch on the characteristics of the time-interleave pipeline ADC,the insensitive timing-skew sample hold circuit were proposed. The ADC was designed using SMIC 0. 13 μm CMOS process,with the area of the core circuit of 1. 6 mm × 1. 3 mm. The test results show that with a sampling frequency of 200 MS / s and an input of 1 MHz,the spurious-free dynamic range（ SFDR） is 67. 8 d B,the signal to noise-and-distortion ration（ SNDR） is 55. 7 d B,the figure of merit（ Fo M） is 1. 07 p J / conv.,and the power dissipation is 107 m W.

关 键 词：A/D转换器(ADC) 时间交织 流水线 运算放大器共享 时序扭曲 

分 类 号：TN792[电子电信—电路与系统]