全数字硬件化正交锁相环建模与分析  

Modeling and Analysis of All-digital Full-hardware Quadrature Phase-locked Loop

作　　者：刘亚静[1] 范瑜[1] 

机构地区：[1]北京交通大学电气工程学院,北京100044

出　　处：《电工技术学报》2015年第15期148-155,共8页Transactions of China Electrotechnical Society

基　　金：国家自然科学基金(51407005;51377009);高等学校博士学科点专项科研基金(20130009120032);中央高校基本科研业务费(2013JBM084)资助

摘　　要：针对FPGA/ASIC的全定制特性带来的字长优化问题,提出一种基于FPGA/ASIC的全数字硬件化正交锁相环字长建模方法。首先,利用稳定性判据和卷积分别建立系数和内部变量的整数字长模型;然后,依据系统灵敏度及L2范数理论分别对系数和内部变量的小数字长建模,从而只需设定系数准确度指标ε和变量准确度指标ζ,即可设计出满足要求的全数字硬件化正交锁相环,保证在消耗最少资源的前提下,有效避免溢出错误和抑制有限字长效应;最后通过实验,验证了所提模型的可靠性。The word-length modeling method for all-digital full-hardware （ADFH） quadrature phase-lockedloop （QPLL） that is implemented with field programmable gate array （FPGA） or application specific integrated circuits （ASICs） is proposed for word-length optimization brought by full-customized FPGA/ASIC. The integerword-length model of the coefficients and the internal variables are built using stability criterion and convolution respectively. Then, the coefficient and internal variable fraction word-length model are constructed in accordancewith the system sensitivity theory and norm2 separately. So the ADFH QPLL can be designed using the proposed method with predefined coefficient precision parameterε and variable precision parameter ζ. The method caneffectively avoid overflow errors and finite-word-length effect with minimum cost. Simulation and experiment results verify the validity of the proposed model.

关 键 词：正交锁相环 全数字硬件化 字长模型 有限字长效应 

分 类 号：TM315[电气工程—电机]