模转换系统有效位数超差分析  

Tolerance of Effective Number of Bits in Analog Conversion Systems

作　　者：孙爱中[1] 张琬珍[1] 张斌峰[1] 

机构地区：[1]中国航空工业集团公司西安航空计算技术研究所,陕西西安710065

出　　处：《电子科技》2015年第9期60-62,共3页Electronic Science and Technology

摘　　要：在某弹载计算机的测试验证中,部分模块的数模转换系统会出现有效位数超差现象。通过故障树分析法对影响因素逐一进行分析,确定为正弦波信号频率对数模转换系统有效位数的影响,通过理论分析和对算法的仿真验证,准确定位了故障,通过修改采样时钟电路设计和调整输入信号的供给,解决了有效位数测试超差问题。ENOB-data out of size are found in part of module＇s ADC circuit in the testing of some missile-borne computer. The fault tree analysis is made of the affecting factors one by one, and it is found that the signal source frequency plays an important role in ADC circuits. The fault position is accurately located by theoretical analysis and algorithm simulation. The problem is solved by redesigning clock circuit and changing the input of the signal.

关 键 词：A/D转换电路 有效位数 信号源频率 信噪失真比 快速傅里叶变换 

分 类 号：TN407[电子电信—微电子学与固体电子学]