宽带载波电力线通信协议中信道交织的FPGA实现  

Implementation of Channel Interleaving of Broadband Carrier Power Line Communications Protocol Based on FPGA

作　　者：张利平[1] 魏巍[1,2] 

机构地区：[1]西安邮电大学计算机学院,陕西西安710061 [2]西安邮电大学物联网与两化融合研究院,陕西西安710061

出　　处：《电子科技》2015年第9期74-76,共3页Electronic Science and Technology

基　　金：陕西省教育厅科学研究基金资助项目(12JK0541)

摘　　要：介绍了宽带载波电力线通信协议中用到的信道交织。在此协议的基础上,提出了基于FPGA信道交织模块的设计方案。文中对信道交织的物理层实现方法进行了介绍,该方法是通过ROM读操作和RAM的读写操作来实现信道交织过程,较好地满足了资源和时延的双重要求。This paper introduces channel interleaving of broadband carrier power line communications protocol. On the basis of this protocol, the schemes of designing FPGA-based channel interleaving are presented. The channel interleaving physical layer implementation methods are described in detail and the main idea of the method is to con- trol read operations for the ROM and control read and write operations for the RAM to achieve channel interleaving process, well meeting the dual requirements of resources and delay.

关 键 词：信道交织 FPGA 宽带载波电力线通信 

分 类 号：TN911.22[电子电信—通信与信息系统]