HMAC-MD5的FPGA优化与实现  

FPGA Optimization and Implementation of HMAC-MD5 Algorithm

作　　者：蔡啸[1,2] 李树国[1,2] 

机构地区：[1]清华大学微电子学研究所,北京100084 [2]清华信息科学与技术国家实验室,北京100084

出　　处：《微电子学与计算机》2015年第9期100-104,共5页Microelectronics & Computer

基　　金：国家"八六三"计划(2012AA012402);清华大学自主研发计划(2011Z05116);清华信息科学与技术国家实验室项目(2015年立项)

摘　　要：在信息安全领域,数据完整性和真实性是十分重要的.HMAC-MD5算法是实现数据完整性和真实性验证的一种算法.HMAC-MD5的软件实现性能较低,而它的FPGA硬件实现性能较高.为了提高FPGA实现的性能,提出了一种二合一的结构,处理512bit数据周期数降低至33拍,提高了吞吐率,同时能够支持HMAC-MD5带密钥输入和不带密钥输入、单MD5运算的模式选择.本设计在Stratix III器件上使用QuartusII 13.0进行综合,在使用了预计算、微指令控制器、资源复用等优化策略之后,最终综合出时钟频率为100 MHz,吞吐率达到1.55Gb/s,逻辑资源使用为1 120ALUTs.Data integrity and authenticity are very important in field of information security.HMAC-MD5 algorithm is one of the algorithms that achieve this target.The performance of its software implementation is very low and its FPGA hardware implementation is much higher.For the sake of higher throughput,this paper propose a two-to-one structure.As the result,it costs only 33 cycles to process 5 12 bits data.At the same time,the design support three kinds of mode：HMAC-MD5 computation with Key,HMAC-MD5 computation without key,MD5 computation. The design contains many optimization strategies such as pre-computation, microinstruction controller, the resources reuse etc.After synthesizing by Quartus Ⅱ 13.0 on Stratix Ⅲ devices,the clock frequency reaches 100 MHz,the throughput reaches 1.55 Gb/s and 1 120 ALUTs logic resources have been used.

关 键 词：HMAC-MD5 FPGA 吞吐率 

分 类 号：TN49[电子电信—微电子学与固体电子学]