Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory  

作　　者：李新开 霍宗亮 靳磊 姜丹丹 洪培真 徐强 唐兆云 李春龙 叶甜春 

机构地区：[1]Institute of Microelectronics,Chinese Academy of Sciences

出　　处：《Journal of Semiconductors》2015年第9期79-84,共6页半导体学报（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(Nos.61474137,61176073,61306107)

摘　　要：This work presents a comprehensive analysis of 3D cylindrical junction-less charge trapping memory device performance regarding continuous scaling of the structure dimensions. The key device performance, such as program/erase speed, vertical charge loss, and lateral charge migration under high temperature are intensively studied using the Sentaurus 3 D device simulator. Although scaling of channel radius is beneficial for operation speed improvement, it leads to a retention challenge due to vertical leakage, especially enhanced charge loss through TPO. Scaling of gate length not only decreases the program/erase speed but also leads to worse lateral charge migration. Scaling of spacer length is critical for the interference of adjacent cells and should be carefully optimized according to specific cell operation conditions. The gate stack shape is also found to be an important factor affecting the lateral charge migration. Our results provide guidance for high density and high reliability 3D CTM integration.This work presents a comprehensive analysis of 3D cylindrical junction-less charge trapping memory device performance regarding continuous scaling of the structure dimensions. The key device performance, such as program/erase speed, vertical charge loss, and lateral charge migration under high temperature are intensively studied using the Sentaurus 3 D device simulator. Although scaling of channel radius is beneficial for operation speed improvement, it leads to a retention challenge due to vertical leakage, especially enhanced charge loss through TPO. Scaling of gate length not only decreases the program/erase speed but also leads to worse lateral charge migration. Scaling of spacer length is critical for the interference of adjacent cells and should be carefully optimized according to specific cell operation conditions. The gate stack shape is also found to be an important factor affecting the lateral charge migration. Our results provide guidance for high density and high reliability 3D CTM integration.

关 键 词：3D charge trapping devices vertical charge loss lateral charge migration semiconductor device simu-lation 

分 类 号：TP333[自动化与计算机技术—计算机系统结构]