On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS  

作　　者：任志雄 张科峰 刘览琦 李聪 陈晓飞 刘冬生 刘政林 邹雪城 

机构地区：[1]School of Optical and Electronic Information,Huazhong University of Science and Technology

出　　处：《Journal of Semiconductors》2015年第9期105-114,共10页半导体学报（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(No.61076030)

摘　　要：Three linear CMOS power amplifiers （PAs） with high output power （more than watt-level output power） for high data-rate mobile applications are introduced. To realize watt-level output power, there are two 2.4 GHz PAs using an on-chip parallel combining transformer （PCT） and one 1.95 GHz PA using an on-chip series combining transformer （SCT） to combine output signals of multiple power stages. Furthermore, some linearization techniques including adaptive bias, diode linearizer, multi-gated transistors （MGTR） and the second harmonic control are applied in these PAs. Using the proposed power combiner, these three PAs are designed and fabricated in TSMC 0.18 μm RFCMOS process. According to the measurement results, the proposed two linear 2.4 GHz PAs achieve a gain of 33.2 dB and 34.3 dB, a maximum output power of 30.7 dBm and 29.4 dBm, with 29% and 31.3% of peak PAE, respectively. According to the simulation results, the presented linear 1.95 GHz PA achieves a gain of 37.5 dB, a maximum output power of 34.3 dBm with 36.3% of peak PAE.Three linear CMOS power amplifiers （PAs） with high output power （more than watt-level output power） for high data-rate mobile applications are introduced. To realize watt-level output power, there are two 2.4 GHz PAs using an on-chip parallel combining transformer （PCT） and one 1.95 GHz PA using an on-chip series combining transformer （SCT） to combine output signals of multiple power stages. Furthermore, some linearization techniques including adaptive bias, diode linearizer, multi-gated transistors （MGTR） and the second harmonic control are applied in these PAs. Using the proposed power combiner, these three PAs are designed and fabricated in TSMC 0.18 μm RFCMOS process. According to the measurement results, the proposed two linear 2.4 GHz PAs achieve a gain of 33.2 dB and 34.3 dB, a maximum output power of 30.7 dBm and 29.4 dBm, with 29% and 31.3% of peak PAE, respectively. According to the simulation results, the presented linear 1.95 GHz PA achieves a gain of 37.5 dB, a maximum output power of 34.3 dBm with 36.3% of peak PAE.

关 键 词：CMOS LINEARITY power combiner TRANSFORMERS power amplifier 

分 类 号：TN722.75[电子电信—电路与系统] TN73