寄存器传输级间歇故障注入平台  

Intermittent fault injection platform implemented in register transfer level

作　　者：王超[1] 张伟[1] 

机构地区：[1]北京信息科技大学计算机学院,北京100101

出　　处：《北京信息科技大学学报（自然科学版）》2015年第4期46-50,共5页Journal of Beijing Information Science and Technology University

基　　金：北京市教委青年拔尖人才培育计划项目(CIJ&TCD201504057)

摘　　要：超大规模集成电路进入深亚微米时代,晶体管特征尺寸缩小,栅氧化物变薄,门限电压降低,金属互联尺寸已减小到极限,导致处理器硬件故障易感性迅速攀升,迫切需要高效灵活的故障注入技术,对处理器系统可靠性进行验证评估。提出采用Verilog PLI框架实现故障注入仿真平台,对OpenSPARC T2处理器寄存器传输级模型实施故障注入,观察分析故障由结构级到达应用级的传播过程。量化分析了硬件故障对软硬件系统的影响程度,以及故障模型参数对系统影响的比较。As ultra-large scale integration circuit has approached into deep sub micron era,efficient and flexible fault injection technologies for reliability assessment of high performance computing system are desperately needed due to feature size shrinking,gate oxide thinning,threshold voltage dropping and interconnection size reaching physical limitation. In this paper,a fault injection tool based on Verilog PLI framework,named RTFIP,is developed. Upon RTFIP,register transfer level fault injection experiments are implemented into Open SPARC T2 processor prototype,and consequently,the propagation process through RTL-level to architectural level and to application level is revealed. As a result,quantitative analysis of hardware faults is approached in accordance with impaction of fault model parameters.

关 键 词：硬件故障 故障注入 RTL模型 可靠性 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构]