一种容错可逆的通用移位寄存器设计  

Design of fault tolerant universal shift register using reversible logic

作　　者：杨洁[1] 汤其妹 陈付龙[1] 齐学梅[2] 叶和平[2] 

机构地区：[1]安徽师范大学数学计算机科学学院,安徽芜湖241003 [2]安徽师范大学网络与信息安全工程技术研究中心,安徽芜湖241003

出　　处：《量子电子学报》2015年第5期600-606,共7页Chinese Journal of Quantum Electronics

基　　金：国家自然科学基金项目(61370050);安徽省自然科学基金项目(1308085QF118);安徽省高校省级自然科学研究项目重点项目(KJ2014A084);安徽师范大学创新基金项目(2013CXJJ01)资助

摘　　要：为了使计算系统具有低功耗和容错能力，基于可逆逻辑设计了一种容错的通用移位寄存器。提出了一种新型的容错可逆逻辑门（Parity-preserving Dflip—flopgate，PP—DFG），利用它和存在的容错门，完成了寄存器和多路数据选择器的设计。综合上述模块，构建了容错可逆的通用移位寄存器电路，用Verilog硬件描述语言建模，仿真显示电路逻辑结构正确。同现有电路相比，根据量子代价、延迟和无用输出对其进行性能评估，结果表明该电路不仅具有容错功能，而且性能提高了16％-48％。设计的电路可作为一种重要的存储元件应用于未来的低功耗计算系统。In order to make the computing system with low power consumption and fault-tolerant ability, a fault-tolerant universal shift register was designed using reversible logic. A new reversible fault-tolerant gate named Parity preserving D flip_flop gate （PP_DFG） was proposed. Some circuits such as register and multiplexer were designed using PP_DFG and existing gates. Based on the above modules, the fault-tolerant reversible universal shift register was built. It was modeled in Verilog hardware description language for verification. Simulation results indicate that its logic structure is correct. Compared with the existing ones in terms of quantum cost, delay and garbage outputs, the proposed circuit not only supports fault-tolerant but also has 16% - 48% performance improvement. This circuit can be used as an important storage element applied in future low-power computing system.

关 键 词：量子计算 可逆逻辑 容错 PP_DFG门 移位寄存器 仿真 

分 类 号：TN91[电子电信—通信与信息系统]