基于混合原型平台的UARTIP核设计与验证  

Design and verification of UART IP core based on hybird ptototyping platform

作　　者：赵新超[1] 陈岚[1] 冯燕[1] 彭智聪[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《电子技术应用》2015年第10期39-42,共4页Application of Electronic Technique

摘　　要：传统的软硬件设计方法已无法满足So C快速验证的应用需求。针对此现状,阐述了虚拟平台与硬件平台相结合的混合原型验证技术,主要介绍了UART IP混合验证方案,分析了UART IP核协议、功能模块设计以及FPGA平台搭建,最后通过构建虚拟平台和编写测试脚本,对IP核进行混合原型验证。验证结果表明,该IP核复用性好,完全可以应用于So C设计中。So far, the hardware and software design in traditional method is unable to meet the application requirements of fast SoC verification. In this situation, the mixed prototyping verification technology is provided which comprised of the virtual platform and the hardware platform. This paper mainly introduces the hybrid replication scheme of UART IP , analysis of the UART IP core protocol, the design of function modules, and the establishment of FPGA platform. Finally, the UART IP core is verified in hybird prototyping method by constructing a virtual platform and writing testsbench. According to the verification results, the IP core is of good reusability and can be applied in SoC design.

关 键 词：UART IP核验证 混合原型平台 硬件原型 虚拟原型 

分 类 号：TN402[电子电信—微电子学与固体电子学]