一种分步式Dual slope ADC的研究与设计  

Design of a new subranged dual slope A/D converter

作　　者：杜微[1] 李荣宽[1] 

机构地区：[1]电子科技大学电子工程学院电路与系统系,四川成都611731

出　　处：《电子技术应用》2015年第10期45-48,共4页Application of Electronic Technique

摘　　要：介绍了一种分步式Dual slope ADC,并且详细介绍了此结构提出的理论基础、电路的具体结构和仿真结果。该Dual slope ADC的系统时钟为1 MHz,输入电压范围为0.5 V^4.5 V,电源电压为5 V。相对于传统的Dual slope ADC,此分步式Dual slope ADC不但可以达到更高的分辨率,而且弥补了传统的Dual slope ADC的缺点,即对于全集成电路的大分布电容的要求以及高分辨率转换时间过长,使得此新型模数转换器还具有速度快(远远快于双积分ADC的速度)的优点。This paper presents a new architecture of the accurate dual slope analog-to-digital converter. This architecture not only has a higher resolution and a lower conversion time than traditional dual slope analog-to-digital converter but also solve the prob- lem of large capacitance in integrated circuit, the device has a system clock frequency of 1 MHz for a supply voltage of 5 V with an input voltage from 0.5 V to 4.5 V. Experimental results are given to confirm the operation of the proposed dual slope ADC.

关 键 词：双积分A/D转换器 复用 自动补偿 高分辨率 

分 类 号：TN453[电子电信—微电子学与固体电子学]