Hybrid Aging Delay Model Considering the PBTI and TDDB  

作　　者：Yong Miao Mao-Xiang Yi Gui-Mao Zhang Da-Wen Xu 

机构地区：[1]the School of Electronic Science and Applied Physics, Hefei University of Technology

出　　处：《Journal of Electronic Science and Technology》2015年第3期276-281,共6页电子科技学刊（英文版）

基　　金：supported by the National Natural Science Foundation of China under Grant No.61371025 and No.61274036

摘　　要：With a 45 nm process technique, the shrinking silicon feature size brings in a high-k/metal gate which significantly exacerbates the positive bias temperature instability （PBTI） and time-dependent dielectric breakdown （TDDB） effects of a NMOS transistor. However, previous works presented delay models to characterize the PBTI or TDDB individually. This paper demonstrates that the delay caused by the joint effects of PBTI and TDDB widely differs from the cumulated result of the delay caused by the PBT｜ and TDDB, respectively, with the experiments on an inverter chain. This paper proposes a hybrid aging delay model comprising both the PBTI and TDDB effects by analyzing the relationship between the aging propagation delay and the inherent delay of the gate. Experimental results on the logic gates under 45 nm, 32 nm, 22 nm, and 16 nm CMOS technologies show that the maximum error between the proposed model and the actual value is less than 2.5%, meanwhile the average error is about 1.5%.With a 45 nm process technique, the shrinking silicon feature size brings in a high-k/metal gate which significantly exacerbates the positive bias temperature instability （PBTI） and time-dependent dielectric breakdown （TDDB） effects of a NMOS transistor. However, previous works presented delay models to characterize the PBTI or TDDB individually. This paper demonstrates that the delay caused by the joint effects of PBTI and TDDB widely differs from the cumulated result of the delay caused by the PBT｜ and TDDB, respectively, with the experiments on an inverter chain. This paper proposes a hybrid aging delay model comprising both the PBTI and TDDB effects by analyzing the relationship between the aging propagation delay and the inherent delay of the gate. Experimental results on the logic gates under 45 nm, 32 nm, 22 nm, and 16 nm CMOS technologies show that the maximum error between the proposed model and the actual value is less than 2.5%, meanwhile the average error is about 1.5%.

关 键 词：Circuit aging positive biastemperature instability time-dependent dielectricbreakdown. 

分 类 号：TN386[电子电信—物理电子学]