面向多核的ECC加速阵列研究与设计  

Research and Design of ECC Acceleration Array for Multi-core

作　　者：王威[1] 严迎健 李博[1] 李伟[1,2] 

机构地区：[1]解放军信息工程大学,河南郑州450001 [2]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《微电子学与计算机》2015年第10期41-45,49,共6页Microelectronics & Computer

基　　金：国家自然科学基金(61404175)

摘　　要：为了使密码多核处理器支持ECC密码算法,提取ECC运算操作特征,设计了一种面向密码多核处理器的ECC加速阵列结构,可实现640bit以内任意长度的双域(素域和二元域)ECC密码算法,有效支持高并行度的ECC加速算法和多ECC算法并行计算.在CMOS 0.18μm工艺库下综合并布局布线,电路最大时钟频率238 MHz,和其他文献相比,此算法的运算速度有所提高,算法支持范围更广.In order to make cipher multi-core processor support ECC eryptographic algorithms, the ECC arithmetic operation characteristics are extracted, and a ECC acceleration array structure for cipher multi-core processor is designed, which can realize dual-domain（prime field and binary field） ECC cryptographic algorithms of arbitrary length within 640 bit. It effectively supports high parallelism degree of ECC algorithms and multi-ECC algorithms parallel accelerating calculation. Implemented in CMOS 0. 18μm technology, circuit maximum clock frequency can reach at 238 MHz. Compared with other literatures, algorithms computing speed is improved and algorithms is supported for a wider range.

关 键 词：密码多核处理器 ECC密码算法 加速阵列 双域可伸缩 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]