A single-ended 10-bit 200 kS/s 607 μ W SAR ADC with an auto-zeroing offset cancellation technique  

作　　者：顾蔚如 吴奕旻 叶凡 任俊彦 

机构地区：[1]State Key Laboratory of ASIC & System [2]Microelectronics Science and Technology Innovation Platform,Fudan University

出　　处：《Journal of Semiconductors》2015年第10期123-129,共7页半导体学报（英文版）

基　　金：Project supported by the National Science and Technology Support Program of China(No.2012BAI13B07);the National Science and Technology Major Project of China(No.2012ZX03001020-003)

摘　　要：Thispaperpresentsasingle-ended8-channel 10-bit200kS/s 607 #W synchronous successiveapproxi- mation register （SAR） analog-to-digital converter （ADC） using HLMC 55 nm low leakage （LL） CMOS technology with a 3.3 V/1.2 V supply voltage. In conventional binary-encoded SAR ADCs the total capacitance grows expo- nentially with resolution. In this paper a CR hybrid DAC is adopted to reduce both capacitance and core area. The capacitor array resolves 4 bits and the other 6 bits are resolved by the resistor array. The 10-bit data is acquired by thermometer encoding to reduce the probability of DNL errors which are typically present in binary weighted architectures. This paper uses an auto-zeroing offset cancellation technique that can reduce the offset to 0.286 mV. The prototype chip realized the 10-bit SAR ADC fabricated in HLMC 55 nm CMOS technology with a core area of 167 × 87 μm2. It shows a sampling rate of 200 kS/s and low power dissipation of 607/μW operates at a 3.3 V analog supply voltage and a 1.2 V digital supply voltage. At the input frequency of 10 kHz the signal-to-noise-and- distortion ratio （SNDR） is 60.1 dB and the spurious-free dynamic range （SFDR） is 68.1 dB. The measured DNL is ±0.37/-0.06 LSB and INL is ±0.58/-0.22 LSB.Thispaperpresentsasingle-ended8-channel 10-bit200kS/s 607 #W synchronous successiveapproxi- mation register （SAR） analog-to-digital converter （ADC） using HLMC 55 nm low leakage （LL） CMOS technology with a 3.3 V/1.2 V supply voltage. In conventional binary-encoded SAR ADCs the total capacitance grows expo- nentially with resolution. In this paper a CR hybrid DAC is adopted to reduce both capacitance and core area. The capacitor array resolves 4 bits and the other 6 bits are resolved by the resistor array. The 10-bit data is acquired by thermometer encoding to reduce the probability of DNL errors which are typically present in binary weighted architectures. This paper uses an auto-zeroing offset cancellation technique that can reduce the offset to 0.286 mV. The prototype chip realized the 10-bit SAR ADC fabricated in HLMC 55 nm CMOS technology with a core area of 167 × 87 μm2. It shows a sampling rate of 200 kS/s and low power dissipation of 607/μW operates at a 3.3 V analog supply voltage and a 1.2 V digital supply voltage. At the input frequency of 10 kHz the signal-to-noise-and- distortion ratio （SNDR） is 60.1 dB and the spurious-free dynamic range （SFDR） is 68.1 dB. The measured DNL is ±0.37/-0.06 LSB and INL is ±0.58/-0.22 LSB.

关 键 词：analog-to-digital converter CR hybrid DAC thermometer encoding auto-zero offset cancellation successive approximation register 

分 类 号：TN792[电子电信—电路与系统]