12位电阻型DAC与失调自校正缓冲器的设计  

Design of a 12 Bit Resistive Divider DAC and Offset-Auto-Corrected Buffer

作　　者：彭超[1] 鲁征浩[1] 徐大诚[1] 

机构地区：[1]苏州大学电子信息学院微电子系,江苏苏州215000

出　　处：《微电子学》2015年第5期560-563,共4页Microelectronics

基　　金：国家自然基金重点项目(61434003)

摘　　要：设计了一种基于TSMC 0.18μm 5V/1.8V CMOS工艺的12位电阻型DAC和缓冲器。该DAC采用两级电阻分压计结构,并提出了一种降低级间负载效应的方法。缓冲器运用自归零校正技术来校正失调,实现了轨到轨的输入和输出。在驱动3kΩ电阻和15nF电容负载时,测得芯片最大失调电压为600μV。在100Hz数据刷新率下,信噪比(SNR)为68.6dB,无杂散动态范围(SFDR)为66.4dB。Based on TSMC 0.18 μm 5 V/1.8 V CMOS process, a 12 bit resistive divider digital-to-analog converter with buffer was proposed. An architecture of two stage resistive dividers was employed, and a method of reducing load effect between different stages was proposed. The rail-to-rail input/output buffer was used to correct the offset by auto-zeroed correction technology. The chip test results showed that the maximum offset was 600μV at a load of 3 kΩ resistor and 15 nF capacitor. The SNR was 68.6 dB, and the SFDR was 66.4 dB at a data update rate of 100 Hz.

关 键 词：数模转换器 自归零校正 缓冲器 电容负载 

分 类 号：TN432[电子电信—微电子学与固体电子学]