HR-2 DSP核的周期精度模拟器设计  

DESIGNING CYCLE ACCURATE SIMULATOR FOR HR-2 DSP

作　　者：吴紫盛 李源[1] 杨群[1] 何虎[1] 

机构地区：[1]清华大学微电子学研究所,北京100084

出　　处：《计算机应用与软件》2015年第10期82-85,共4页Computer Applications and Software

基　　金：核高基重大专项(2012ZX01034001-002)

摘　　要：HR-2(华睿2号)是核高基重大专项中面向雷达应用的一款高性能数字信号处理器。为了给HR-2 DSP核开发提供一款模拟器以进行性能评测和优化指导,并提前进行多核架构的探索,提出一种高效的周期精度软件模拟器建模方法。首先分析该处理器的流水线结构,指令动态执行和分支预测机制,然后使用LISA语言在PD(Processor Designer)工具中对该处理器的流水线、指令集和寄存器重命名等内容进行设计实现,从而开发出HR-2 DSP核的周期精度模拟器模型。实验结果表明,基于该建模方法开发的模拟器周期精度误差在10%以内,可以进行高精度的处理器性能评测和各种模式下的架构探索。HR-2 is a high-performance digital signal processor （DSP）for radar applications in national major special projects of core elec-tronic devices.In order to provide a simulator for HR-2 DSP development to carry out performance evaluation and optimisation guidance as well as to implement in advance the exploration of multi-core architecture,we proposed an efficient cycle accurate simulator modelling meth-od.First,we analysed processor’s pipeline architecture,dynamic instruction execution and branch prediction mechanisms,then we used LI-SA language to have designed and implemented on processor designer （PD）the contents of pipeline,instruction set and register renaming of processor,thereby developed the cycle accurate simulator model of HR-2 DSP.Experimental results showed that the simulator developed by this modelling method could obtain more than 90% cycle accuracy,and processors’performance evaluation and architecture exploration in different patterns could be performed with high accuracy.

关 键 词：数字信号处理器 模拟器 周期精度 流水线 LISA 语言 

分 类 号：TP302.1[自动化与计算机技术—计算机系统结构]