基于随机延时的嵌入式CPU抗DPA硬件架构  

AN ANTI-DPA HARDWARE ARCHITECTURE OF EMBEDDED CPU BASED ON RANDOM DELAY

作　　者：段凌霄 孟建熠[2] 严晓浪[1] 

机构地区：[1]浙江大学电气工程学院,浙江杭州310027 [2]浙江大学信息与电子工程学系,浙江杭州310027

出　　处：《计算机应用与软件》2015年第10期220-222,239,共4页Computer Applications and Software

基　　金：国家核高基重大专项项目(2009ZX01030-001-002)

摘　　要：针对嵌入式CPU运行加解密算法时产生的功耗边道效应问题,提出了一种基于随机延时的抗DPA攻击的嵌入式处理器架构。该架构在处理器前级流水级中插入随机的等待延时,在时间轴上对每一次程序运行的功耗轨迹进行干扰,从而达到抗DPA攻击目的。实验表明,该架构具有良好的抗差分功耗分析的特性,且硬件电路的设计复杂度较低。Embedded CPU will cause side channel effects of power consumption when running encryption and decryption algorithms.In light of this issue,we proposed a random delay-based embedded processor architecture,which is able to resist DPA attacks.In the proposed architecture,random waiting delay will be inserted into preceding pipeline stage to interfere with the track of power consumption in timeline for every program running,so that to achieve the goal of DPA attacks resistant.Experiments show that this architecture has a good characteristic in resisting differential power analysis,moreover it also has lower design complexity in hardware circuit.

关 键 词：差分功耗分析(DPA) DES 随机延时插入 

分 类 号：TP393[自动化与计算机技术—计算机应用技术]