高速时钟的抖动分析  

Analysis on Jitter of High-Speed Clock

作　　者：张彦[1] 刘军峰[1] 马婷[1] 

机构地区：[1]中国空间技术研究院西安分院,西安710000

出　　处：《空间电子技术》2015年第4期58-61,共4页Space Electronic Technology

摘　　要：在高速数模转换电路里,如何降低由时钟抖动引起的模数转化误差,已成为高速数模转换电路设计的关键问题。文章结合输入信号频率和抖动与信噪比的关系,给出了如何根据相位噪声和抖动参数来选用器件的建议。针对如何降低系统时钟的抖动,分析了引入时钟抖动的主要因素给出了可降低这些影响因素的推荐电路。How to reduce the error caused by jitter of clock is the key issues in the designs of high-speed digital-to-ana- log conversion circuit. Based on the relationship of between input signal frequency ,jitter and SNR, the paper presents the suggestions on the choices of deviee according to the relative noise and the jitter parameters. The main factors that may cause jitter of clock were analyzed. Certain electric circuit was recommended to reduce the influence of these factors.

关 键 词：时钟抖动 阻抗匹配 数模转换 

分 类 号：TN85[电子电信—信息与通信工程]